The present invention relates to a feedback shift register for generating digital signals representing pseudo-random number sequences comprising n-stages and exclusive OR-circuits in the feedback logic, as well as comprising a clock-pulse generator.
A. Wolf "Me.beta.technik fur das BISDN" [Measuring Technique for the BISDN], VDE Publishers, 1992, pp. 72-75 or U. Tietze/Ch. Schenk "Halbleiter-Schaltungstechnik" [Semiconductor Circuit Engineering], Springer Publishers 1976, pp. 590-593 disclose one such feedback shift register. FIG. 1 depicts a known shift register 1 of this type that includes five stages 2, 3, 4, 5 and 6, each constituted by for example, a D-flip-flop. As is apparent from FIG. 1, the shift register 1 goes through a feedback loop, an exclusive OR-gate 7 being arranged between the stages 3 and 4. The operation of this register can be expressed by the following generator polynomial G.sub.KKF (x): EQU G.sub.KKF (x)=x.sup.0 +x.sup.2 +x.sup.5 =x.sup.5 +x.sup.2 +1(1)
This generator polynomial G.sub.KKF (x) is a so-called irreducible polynomial with the degree g=5; the period of a 2.sup.5 -m-sequence able to be generated with it as a pseudo-random number sequence amounts to 2.sup.g -1=31.
For the sake of having a simplest possible description, neither the clock-pulse generator common to all stages nor the customary blocking protection are depicted in the case of the known shift register shown in FIG. 1. In the case of the known shift register, all stages receive the same clock signal, through which means the contents i.sub.1 (x).x.sup.0, i.sub.2 (x).x.sup.1, etc. of the individual stages 2 through 6 change with every clock signal. The contents of the individual stages can be expressed by the polynomial I(x) indicated in the following equation (2): EQU I(x)=x.sup.4 .multidot.i.sub.5 +x.sup.3 .multidot.i.sub.4 +x.sup.2 .multidot.i.sub.3 +x.sup.1 .multidot.i.sub.2 +x.sup.0 .multidot.i.sub.1( 2 )
Here, the state in which all stages have a "0" contents is excluded.
In a generally known manner, the contents of the shift register make up the rows of a binary Galois field, and can generally be expressed by the following relation (3) EQU x.sup.i mod G.sub.KKF (x), (3)
when a "1" is input for i=0 in the first stage (x.sup.0). The states depicted in FIG. 2 result then for the contents of the stages 2 through 6 when a shift register in accordance with FIG. 1 is used. From x.sup.31 on, the states of the individual stages 2 through 6 repeat themselves because of the period of 31 of the 2.sup.5 -m-sequence. One obtains the 2.sup.5 -m-sequence as a binary sequence of numbers: EQU c.sub.0 (n)={0000100101100111110001101110101}, (4)
which is identical to the contents of the stage 6.
An inadequacy of the digital signals produced with the known shift register is that they have a period of 2.sup.n -1 where n denotes the number of stages of the shift register. Thus in the case of the depicted 2.sup.5 -m-sequence the period duration is 31. Therefore, the thus generated digital signals are not easily suited for further digital processing using customary digital measured-value processing devices. This is true, for example, when a fast Fourier transform is supposed to be made, for which it is a condition that the data record has 2.sup.n values.